Semiconductor device and method for fabricating the same

ABSTRACT

A method of fabricating a semiconductor device that may include at least one of the following steps: Forming a lower metal wiring on and/or over a semiconductor substrate. Forming an interlayer insulating film having a damascene hole on and/or over the semiconductor substrate and the lower metal wiring. Forming an anti-diffusion film on and/or over the exposed lower metal wiring below the damascene hole and/or on side surfaces of the damascene hole. Selectively removing the anti-diffusion film formed on and/or over the exposed lower metal wiring at the bottom of the damascene hole using a plasma process that uses an inert gas.

This application claims priority under 35 U.S.C. 119 to Korean PatentApplication No. P10-2007-0062804 (filed Jun. 26, 2007), which is herebyincorporated by reference in its entirety.

BACKGROUND

Embodiments relates to a semiconductor device fabricated using adamascene process and/or a method of fabricating the same. Due toincreasing complexity of integrated circuits, multilevel interconnectingprocesses may be desirable when fabricating semiconductor devices. Tofulfill high integration-degree and/or high speed requirements ofintegrated circuits, a Copper (Cu) dual-damascene process may be used. ACu dual-damascene process may be used to form interconnecting wirings ina metal-interlayer dielectric film having a relatively low dielectricconstant k. Since copper has a relatively low resistance and relativelylow electron transfer resistance, relatively low dielectric materialsmay be used to minimize negative RC delay effects of metal wiringconnections. Using copper (Cu) wiring instead of aluminum (AL) wiring asa material choice may improve resistance characteristics. However, inaddition to general material choices, it may be desirable to furthermaximize resistance characteristics in wiring as fabricated devicesbecome smaller.

Often times, Cu dual-damascene processes have a drawback of having arelatively large contact resistance of vias that connect lower metalwiring (e.g. due to byproducts, such as polymers, etc. in the vias). Insome circumstances, proper formation of the vias is impractical and/orvery difficult, which may result in relatively low yield and/orrelatively poor device reliability.

SUMMARY

Embodiments relate to semiconductor devices and/or methods offabricating semiconductor devices, which may have relatively low contactresistance in vias formed in a damascene process, may minimizebyproducts present in vias, may improve gap-fill capabilities of uppermetal wirings, and/or minimize defect rates.

Embodiments relate to a method of fabricating a semiconductor devicethat may include at least one of the following steps: Forming a lowermetal wiring on and/or over a semiconductor substrate. Forming aninterlayer insulating film having a damascene hole on and/or over thesemiconductor substrate and the lower metal wiring. Forming ananti-diffusion film on and/or over the exposed lower metal wiring at thebottom of the damascene hole and/or on a side surface region of thedamascene hole. Selectively removing the anti-diffusion film formed onand/or over the exposed lower metal wiring at the bottom of thedamascene hole using a plasma process that uses an inert gas.

In embodiments, a semiconductor device may include at least one of: Alower metal wiring formed on and/or over a semiconductor substrate. Aninterlayer insulating film formed on and/or over the semiconductorsubstrate and the lower metal wiring; the interlayer insulating film mayhave a damascene hole formed to correspond to the lower metal wiring. Ananti-diffusion film formed on and/or over side surfaces of the damascenehole. An upper metal wiring formed on and/or over the lower metal wiringat the bottom of the damascene hole and on the anti-diffusion film.

DRAWINGS

Example FIG. 1 illustrates a sectional view of a semiconductor devicefabricated by a damascene process, in accordance with embodiments.

Example FIGS. 2 to 5 illustrate process sectional views of asemiconductor device, in accordance with embodiments.

Example FIGS. 6A to 6E are photographs illustrating actual coupledconfigurations of upper and lower metal wirings obtained by a TEM underconditions of different punch through times, in accordance withembodiments.

Example FIG. 7 illustrates a view showing gap-fill characteristics of anupper metal wiring under conditions of different punch through times, inaccordance with embodiments.

Example FIG. 8 illustrates a graph showing a variation of contactresistance according to a variation of punch through time on the basisof a via critical dimension (CD) of 0.19 μm, in accordance withembodiments.

Example FIG. 9 illustrates a graph showing a variation of defect ratesaccording to a variation of punch through time, in accordance withembodiments.

DESCRIPTION

Example FIG. 1 illustrates a sectional view of a semiconductor devicefabricated by a damascene process, in accordance with embodiments. Asemiconductor device may include lower metal wiring 12 made of Cu or asimilar material. Lower metal wiring 12 may be formed on and/or oversemiconductor substrate 10. Lower metal wiring 12 may be surrounded byanti-diffusion film 13. In embodiments, anti-diffusion film 13 mayprevent lower metal wiring 12 from being diffused into substrate 10. Inembodiments, lower metal wiring 12 may be formed on a lower insulatingfilm (e.g. a lower insulating film may be formed on and/or oversemiconductor substrate 10). In embodiments, processing on and/or over alower insulating film may be similar to processing on and/or oversemiconductor substrate 10. Accordingly, for purposes of illustration, alower insulating film may be substituted for semiconductor substrate 10with regard to processing.

A semiconductor device may include interlayer insulating film 18 formedon and/or over semiconductor substrate 10, in accordance withembodiments. Interlayer insulating film 18 may have a damascene holeconnecting to lower metal wiring 12. Anti-diffusion film 16 may beformed on side surfaces of the damascene hole. To form theanti-diffusion film 16, a desired material may be deposited and then aportion of the anti-diffusion film 16 that is at the bottom of thedamascene hole may be removed, in accordance with embodiments. Asillustrated in FIG. 1, a semiconductor device may have no anti-diffusionfilm 16 between lower metal wiring 12 and upper metal wiring 20, inaccordance with embodiments. Anti-diffusion film 16 may serves toprevent copper atoms of upper copper wiring 20 from being diffused intointerlayer insulating film 18. If copper atoms are significantlydiffused into interlayer insulating film 18, a semiconductor device maysuffer from current leakage.

Metal layer 14 may be formed between upper metal wiring 20 andanti-diffusion film 16. Metal layer 14 may be formed between upper metalwiring 20 and lower metal wiring 12. In embodiments, metal layer 14 maynot be necessary and upper metal wiring 20 may be in direct contact withlower metal wiring 12.

Example FIGS. 2 to 5 illustrate process sectional views of asemiconductor device, in accordance with embodiments. As illustrated inFIG. 2, lower metal wiring 12 may be formed on and/or over semiconductorsubstrate 10, in accordance with embodiments. Interlayer insulating film18 may be formed on and/or over semiconductor substrate 10, wheresemiconductor substrate 10 may include lower metal wiring 12. Interlayerinsulating film 18 may have damascene hole 30. The damascene hole 30 mayinclude trench 32 and/or via 34. Interlayer insulating film 18 may bemade of a relatively low dielectric material having a relatively lowdielectric constant k. In embodiments, interlayer insulating film 18 maybe made of a porous low dielectric film, which may have an especiallylow dielectric constant k. In embodiments, Fluorine-doped-Silica-Glass(FSG) (k=˜3.4) may be deposited on and/or over semiconductor substrate10 and lower metal wiring 12 (e.g. by chemical vapor deposition (CVD)).In embodiments, a portion of deposited FSG corresponding to damascenehole 30 may be removed to form interlayer insulating film 18 having aconfiguration illustrated in FIG. 2. In embodiments, a “via-first”method of first patterning via 34 may be used to fabricate thedual-damascene pattern illustrated in FIG. 2. In embodiments,OrganoSilicate Glass (OSG) (k=˜2.8) (e.g. instead of FSG) may be used toform interlayer insulating film 18.

As illustrated in example FIG. 3, anti-diffusion film 16A may be formedon and/or over exposed lower metal wiring 12 at the bottom of damascenehole 30 and/or exposed interlayer insulating film 18 (e.g. includingside surfaces of damascene hole 30). Anti-diffusion film 16A may beformed by depositing titanium (Ti), titanium nitride (TiN), tungstennitride (Wn), tantalum nitride (TaN), TaN/Ta, and/or similar material.In embodiments, TaN/Ta may be deposited on and/or over interlayerinsulating film 18 inside damascene hole 30 and on and/or over lowermetal wiring 12 using physical vapor deposition (PVD) to from theanti-diffusion film 16A.

As illustrated in example FIG. 4, anti-diffusion film 16A formed onand/or over lower metal wiring 12 at the bottom of damascene hole 30 maybe selectively removed. Anti-diffusion film 16A may be selectivelyremoved by a plasma process using an inert gas (e.g. argon (Ar)). Inembodiments, a plasma process of selectively removing anti-diffusionfilm 16A formed on and/or over lower metal wiring 12 may be referred toas a “punch through”. With implementation of a punch through, it may bepossible to lower contact resistance by removing residues (e.g. polymersand/or impurities). In embodiments, as illustrated in FIG. 4, a portionof lower metal wiring 12A may be removed during implementation of apunch through. In embodiments, a plasma process using Ar may beimplemented under a pressure of approximately 3,000 mT to 6,000 mT, DCpower of approximately 100 W to 1,000 W, AC bias power of approximately100 W to 1,000 W, and/or a temperature of approximately 20° C. to 30° C.

In embodiments, removed material of the anti-diffusion film 16A (e.g.removed during implementation of the punch through) may be re-depositedon the remaining anti-diffusion film 16A (e.g. on the side surfaces ofdamascene hole 30). For example, when anti-diffusion film 16A is made ofTaN/Ta, copper components separated from lower metal wiring 12 as wellas Ta+ and nitride may be removed from anti-diffusion film 16A duringthe punch through and may be re-deposited onto side surfaces of trench32 and via 34 to form anti-diffusion film 16B. In embodiments, formingnew anti-diffusion film 16B via re-deposition may compensate for lossesof anti-diffusion film 16A during the punch through, which may maximizeapplication efficiency of anti-diffusion film 16. Accordingly, inembodiments, this re-deposition may facilitate efficient and effectivedeposition of copper within narrow via 34.

As illustrated in example FIG. 5, after selectively removinganti-diffusion film 16A from lower metal wiring 12, metal layer 14 maybe formed on and/or at the bottom of damascene hole 30 and on sidesurfaces of damascene hole 30, in accordance with embodiments. Inembodiments, metal layer 14 may be the same material as anti-diffusionfilm 16. In embodiments, metal layer 14 may be a different material asanti-diffusion film 16. Metal layer 14 may be formed to compensate fordamage to lower metal wiring 12A during a punch through, in accordancewith embodiments. In embodiments, metal layer 14 may be formed tomaximize adhesive force with copper as a seed during formation of uppermetal wiring 20. Example Table 1 illustrates example thicknesses ofTaN/Ta anti-diffusion film 16 and/or Ta metal layer 14.

TABLE 1 Anti-Diffusion Film Condition TaN Ta Metal Layer (Ta) Thickness5~30 5~30 1~15 (nm)

In embodiments, after forming metal layer 14, upper metal wiring 20 maybe formed (e.g. by Electro-Chemical-Deposition (ECD)), as illustrated inFIG. 1.

In embodiments, implementation time of a plasma process (e.g. punchthrough time) may be adjustable. Shape variations of via 34 and/orgap-fill characteristics of upper metal wiring 20 in relation to punchthrough times may be analyzed using a Transmission Electron Microscope(TEM) and/or a Focused Ion Beam (FIB).

FIGS. 6A to 6E illustrate coupled configurations of lower metal wirings12 and upper metal wiring 20 obtained by a TEM under different punchthrough times, in accordance with embodiments. FIG. 6A illustrates aconfiguration when a punch through is not applied and FIGS. 6B to 6Eillustrate configurations when a punch through is implemented for 25seconds, 35 seconds, 40 seconds, and 45 seconds, respectively, inaccordance with embodiments.

In embodiments, when analyzing electric characteristics by a probetester using four terminals, a profile of via 34 coming into contactwith lower metal wiring 12 is shown in example FIGS. 6A to 6E. Asillustrated in FIGS. 6A to 6E, the longer the punch through time, thedeeper the interaction depth of the lower and upper metal wirings 12 and20 may be, in accordance with embodiments. For example, side surfaces ofdamascene hole 30 may have optimized side coverage.

Example FIG. 7 is a view illustrating gap-fill characteristics of uppermetal wiring 20 under different punch through times, in accordance withembodiments. Anti-diffusion film 16 may be formed by deposition ofTaN/Ta and the punch through may be implemented for 0 seconds (O″), 25seconds (25″), and/or 35 seconds (35″), respectively. FIG. 7 illustratesgap-fill characteristics of a Cu upper metal wiring 20 analyzed using anFIB, in accordance with embodiments. When no punch through is applied(0″), copper voids may occur from a via Critical Dimension (CD) of 0.13μm. However, upon implementation of a punch through, void-less gap-fillmay occur until the via CD reaches about 0.11 μm. A punch through maysubstantially remove residues, such as polymers and/or impurities,present in the via 34. While anti-diffusion film 16 located on lowermetal wiring 12 is removed, the removed material of anti-diffusion film16 may be re-deposited, which may result in improved side coverage ofvia 34.

Example FIG. 8 is a graph illustrating a variation of contact resistanceaccording to variations of punch through times on the basis of a viacritical dimension (CD) of 0.19 μm, in accordance with embodiments. InFIG. 8, the horizontal axis represents contact resistance and thevertical axis represents probability. In examples, a punch through wasimplemented for 0 seconds, 25 seconds, 35 seconds, 40 seconds, and 45seconds, respectively.

In embodiments, as shown in example FIG. 8, when a punch through isapplied, anti-diffusion film 16 at the bottom of damascene hole 30 maybe removed, which may result in minimization of contact resistance ofapproximately 40%. As punch through time is increased, contactresistance may increase by about 0.1 Ω/cnt. For example, as illustratedin FIG. 6, as punch through time is implemented, a contact angle betweenlower metal wiring 12 and anti-diffusion film 16 may be reduced, whichmay reduce the size of via 34.

Example FIG. 9 is a graph illustrating a variation of defect ratesaccording to variations of punch through times, in accordance withembodiments. In FIG. 9, the horizontal axis represents different punchthrough times and the vertical axis represents an average number ofdefects. For example, Bit2Co1 cnt/AVG of the ordinate means an AVeraGe(AVG) number of defective 4M Static Random Access Memories (SRAMs) inwhich two bits are defective in a column direction. Bit2Co1 includesboth Bit2Co1_O (defects in an Odd direction) and Bit2Co1_E (defects inan Even direction).

Defects may occur when via 34 is not properly formed, which may have aneffect on manufacturing yield. As illustrated in FIG. 9, increasing thepunch through time diametrically may minimize defect rate. Defect ratemay be minimized because residues (e.g. polymers or impurities) at thebottom of via 34 may be effectively removed as the punch through isimplemented.

In embodiments, a semiconductor device and/or a method for fabricating asemiconductor device implement a punch through to substantially removeresidues in vias, which may lower contact resistance and/or improve sidecoverage of vias. In embodiments, gap-fill characteristics may beoptimized in an upper metal wiring and/or a defect rate may beminimized, which may result in optimized manufacturing yield. Inembodiments, as punch through time is increased, gap-fill capabilitiesof an upper metal wiring may be optimized and/or contact resistance ofvias may be minimized. In embodiments, byproducts (e.g. polymers presentin the vias) may be removed, which may minimize a defect rate and/oroptimize manufacturing yield.

It will be obvious and apparent to those skilled in the art that variousmodifications and variations can be made in the embodiments disclosed.Thus, it is intended that the disclosed embodiments cover the obviousand apparent modifications and variations, provided that they are withinthe scope of the appended claims and their equivalents.

1. A method comprising: forming a lower metal wiring over asemiconductor substrate; forming an interlayer insulating film over thesemiconductor substrate and the lower metal wiring; forming a damascenehole in the interlayer insulating film, wherein the damascene holeexposes a portion of the lower metal wiring at a bottom of the damascenehole; forming an anti-diffusion film over the lower metal wiring at thebottom of the damascene hole and on side surfaces of the damascene hole;and selectively removing a portion of the anti-diffusion film formedover the lover metal wiring at the bottom portion of the damascene hole.2. The method of claim 1, wherein said selectively removing comprises aplasma process using inert gas.
 3. The method of claim 2, wherein theplasma process is implemented using argon (Ar) as the inert gas under atleast one of: a pressure between approximately 3,000 mT to 6,000 mT; DCpower between approximately 100 W to 1,000 W; AC bias power between 100W and 1,000 W; and temperature between approximately 20° C. and 30° C.4. The method of claim 2, comprising re-depositing material of theanti-diffusion layer that was removed by the plasma process on the sidesurfaces of the damascene hole.
 5. The method of claim 4, comprising:separating a lower metal material from a portion of the lower metalwiring at the bottom of the damascene hole by the plasma process; anddepositing the separated lower metal material on the side surfaces ofthe damascene hole.
 6. The method of claim 5 comprising forming a metallayer over the side surfaces of the damascene hole and over the bottomof the damascene hole, wherein the portion of the metal layer that isformed on the side surfaces is formed over the separated lower metalmaterial that was deposited on the side surfaces.
 7. The method of claim5, wherein thickness of the re-deposited anti-diffusion film materialover the side surfaces of the damascene hole corresponds to theimplementation time of the plasma process.
 8. The method of claim 1,comprising forming a metal layer over the bottom of the damascene holeand over the side surfaces of the damascene hole after said selectivelyremoving the anti-diffusion film.
 9. The method of claim 8, comprisingforming an upper metal wiring by filling metal material in the damascenehole after forming the metal layer.
 10. The method of claim 8, whereinthe metal layer and the anti-diffusion film comprises the same material.11. The method according to claim 8, wherein: the anti-diffusion filmhas a thickness between approximately 10 nm and 60 nm; and the metallayer has a thickness between approximately 1 nm and approximately 15nm.
 12. The method of claim 1, wherein: the lower metal wiring comprisescopper (Cu); and the anti-diffusion film comprises at least one oftitanium (Ti), titanium nitride (TiN), tungsten nitride (Wn), tantalumnitride (TaN), and TaN/Ta.
 13. The method of claim 1, wherein theinterlayer insulating film comprises a low dielectric film having a lowdielectric constant k.
 14. The method of claim 13, wherein the lowdielectric film is a porous low dielectric film.
 15. The method of claim1, wherein said selectively removing the anti-diffusion filmsubstantially simultaneously removes at least one of residues, polymers,and impurities from the damascene hole.
 16. An apparatus comprising: alower metal wiring formed over a semiconductor substrate; an interlayerinsulating film formed over the semiconductor substrate and the lowermetal wiring, wherein the interlayer insulating film has a damascenehole formed which exposes the lower metal wiring; an anti-diffusion filmformed over side surfaces of the damascene hole; and an upper metalwiring formed over the anti-diffusion film and the lower metal wiring ata bottom of the damascene hole.
 17. The apparatus claim 16, comprising ametal layer formed between the upper metal wiring and the anti-diffusionfilm and formed between the upper metal wiring and the lower metalwiring.
 18. The apparatus of claim 16, comprising a lower insulatingfilm formed between the semiconductor substrate and the interlayerinsulating film, wherein the lower metal wiring is formed over the lowerinsulating film.
 19. The apparatus of claim 16, wherein the lower metalwiring comprises copper (Cu).
 20. The apparatus of claim 16, wherein theanti-diffusion film comprises at least one of titanium (Ti), titaniumnitride (TiN), tungsten nitride (Wn), tantalum nitride (TaN), andTaN/Ta.